The primary job function is to work with other team members to define architecture, design, verify wireless SOC containing wireless transceivers, ARM Cortex M other IPs.
Requirements
B.S. M.S. in Electrical Engineering equivalent
Expertise in Verilog System Verilog flow power testability design
Knowledge experience of digital design techniques, including flow control, arbitration, FIFO, ARM Cortex CPU architecture, AXI / AHB bus architecture & protocols, serial interface design concepts (PCI-E, QSPI, I2C, etc…), FIFO, DMA, embedded memory (SRAM, OTP, etc…)
Experience of ASIC low power design techniques including multiple supply domains management, dynamic power/clock scaling, power analysis, UPF, VCLP. knowledge of how to drive the power down through all aspects of development, including chip architecture, micro-architecture, RTL design, physical design.
Hardware firmware co verifications. Synthesis using Synopsys Cadence tools.
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