PDG introduction:
Arm china PDG group design support physical IP on Chinese foundry partners, offers IC designers a wide range of choices from its broad portfolio of arm china owned physical IP. Arm china PDG group physical IP include high-performance, high-density, low-power ultra-low power Logic IP, Embedded Memory Compiler Interface IP feach foundry process technology. These productions ease implementation challenges fadvanced nodes to accelerate core hardening, speed SoC implementation reduce project rise fIC design.
Job Description:
1. Responsible fthe development of physical IP layouts in advance CMOS FinFET process.
2. Perform physical verification(DRC/LVS/Antenna) fstandard cell, memory, IO, from bottom cells to top hierarchy.
3. Capable of developing workflow automation fMemory compiler layout design.
4. Undertake the assignments in a team.
5. Work closely with circuit design engineers to ensure highest quality physical IP layout.
Education Qualification:
1. Bachelor’s degree in related fields such electrical engineering, computer science, physics etc.
2. Should have good understanding of basic CMOS, FinFET SOI process circuits.
3. Experience familiarly in various physical verification checks, like DRC, LVS, ERC, Antenna, Density, ESD, LUP, IREM, etc..
4. Familiar with layout design verification tools(virtuoso, Laker, Caliber).
5. Familiar with process design principle place route effect.
6. Familiar with script language, such as Perl, Python, TCL.
7. Good communication skills, learning competency, self-motivated team spirit.
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