兆芯集成电路 ee jobs (salary & requirements)

岗位职责：
1.test-plan extract test-points according to the Design specification.
2. Build robust simulation testbench using advanced verification methodologies at Block-Level Subsystem-Level to verify correctness of complex ASIC design implementations.
3.Develop accurate testcases fDUT, including both random direct cases.
4.Run RTL gate-level simulation regressions, co-work with designers to debug failures.
5. Conduct function coverage code coverage collection analysis other verification signoff tasks according to signoff checklist.
任职要求：
1. BS in CS/EE/ME, Familiar with ASIC design verification flows.
2. Familiar with design/verification languages such as Verilog SystemVerilog, knowledge of UVM is preferred.
3. Hands on experience of EDA tools such as Xcelium VCS/Verdi is a plus.
4. Knowledge of script language such as Makefile, TCL, shell, Python, Perl is desired.
6. Good English reading/writing communication skills."