工作职责:
1. Define chip level DFT test spec test structure.
2. Be responsible fDFT flow/methodology evolvement, DFT logic implementation verification, including the design, implementation, verification of DFT IP. Covering standard DFT structures such as MBIST, Scan, Boundary Scan, custom DFT IP.
3. Be responsible fpattern generation along with pre-layout simulation/post-layout simulation of each DFT test item.
4. Be responsible fDFT SDC release check, along with DFT related STA, power, IR task forces.
5. Co-work with production testing team, complete ATE bring up/pattern tuning yield improvement work of all DFT test items drive low even zero DPPM.
任职资格:
1. Majin EE related. Master degree with 1+ years’ experience in DFT-related areas.
2. Solid knowledge on ASIC DFT design verification, including JTAG/IJTAG, MBIST, SCAN, ATPG post-simulation.
3. Prefer proficient in RTL coding (Verilog/System Verilog). Demonstrated experience in designing, developing, verifying custom DFT IP (e.g., complex controllers, specialized test access mechanisms, custom BIST engines).
4. Familiar with ASIC design flow, including formal/UPF, synthesis STA.
5. Experienced in DFT EDA tool usage, such as Tessent mbist, scan, VCS/Xcelium DC/PT.
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