上海 ee jobs (salary & requirements)

Requirements:
1.3-5 years of UVM/VIP with SystemVerilog/Verilog experience in high-speed interface projects.
2.Familiarity with SerDes (such as PCIe/Ethernet/MIPI/USB) packet framing rules.
3.Skilled in developing UVM Agents, Scoreboards, Assertions (SVA).
4.Proficiency in Python/Perl fautomated result analysis scripting.
5.Experience in Gate-level Simulation (GLS) timing violation analysis.

Job Description:
1.Directed Random Testcases fprotocol corner-case coverage.
2.Maintain UVM components assist designers in RTL Debugging.
3.Execute daily Regressions perform root-cause analysis on failures.
4.Verify the Controller-PHY digital handshaking flow control stability.
5.Quantify system performance (Bandwidth/Latency) via verification environments.

Requirements:
1.3-5 years of UVM/VIP with SystemVerilog/Verilog experience in high-speed interface projects.
2.Familiarity with SerDes (such as PCIe/Ethernet/MIPI/USB) packet framing rules.
3.Skilled in developing UVM Agents, Scoreboards, Assertions (SVA).
4.Proficiency in Python/Perl fautomated result analysis scripting.
5.Experience in Gate-level Simulation (GLS) timing violation analysis.

Work Location: Expatriate to Zhuhai