Xinyi Technology dft jobs (salary & requirements)

Xinyi Technology dft salary range: 30K - 50K, where 100% of positions earn ¥30-50K以上

***  ? 30-50K ***  ? 50K以上

Xinyi Technology dft salary range: 30K-50K, the most positions earn 50K以上, based on 3 related positions in the past year, as of 2026-10-19

￥30-50K以上

100% of positions earn

Note: the average salary is analyzed based on job postings published by the company. We recommend reviewing it together with position type, education, region and experience.

Xinyi Technology dft salary changes over the years

Note: the data depends on salary samples of online job postings in the corresponding years and does not fully represent the actual situation within the company. For reference only.

Education requirements: 本科 is the most common

100% 本科

What education does Xinyi Technology require for dft positions? 本科占比最多，占100%

Salary by education

本科￥46.7K

Xinyi Technology dft salaries by education: 本科 ¥46.7K.

Experience requirements: 5-10年 is the most common

66.7% 5-10年 33.3% 不限

What experience does Xinyi Technology require for dft positions? 5-10年占比最多，占66.7%，不限占33.3%

Salary by experience

5-10年￥45.0K

Xinyi Technology dft salaries by experience: 5-10年 ¥45.0K.

Xinyi Technology dft hiring regions: mainly 上海

上海￥46.7K 100%(3)

In which cities does Xinyi Technology have offices for dft positions? The main distribution is as follows: 上海 accounts for 100%. Click this module to view the proportions of other cities, based on job postings in the past year. For reference only.

Xinyi Technology dft hiring trends over the years

Xinyi Technology dft changes in hiring volume over the years

What does Xinyi Technology dft do

Based on related job postings of Xinyi Technology in the past year

芯片前中端工程师（Synthesis/STA/DFT）
上海 | 5-10年 | 本科以上 | 2026-03-25
25-50k·15薪

岗位职责：
1. 负责芯片的逻辑综合，形式验证和静态时序分析，跟进后端反馈时序问题
2. 与前端工程师合作，开发SDC，制定DFT并执行综合和DFT过程
3. 和前端设计团队以及后端工程师紧密合作，全芯片SDC集成，并制定后端实现方案；
4. 芯片级timing eco以及timing signoff验收, 产生SDF并协助验证团队进行后仿工作；
5. 维护synthesis/formal/sta相关流程, 脚本自动化，检查各个阶段输出质量,与质量团队一起完成signoff；
6. 拉通前端设计团队协助后端工程师一起做好各种物理检查及功耗分析
7. 熟悉常用ATGP pattern的产生
8. 与后端工程师一起合作解决基于低功耗流程带来的各种涉及到前端，后端的各种电源域相关物理问题
任职要求：
1. 本科及以上，5年以上相关工作经验，真正负责过量产芯片的前中端工作
2. 精通Verilog语言，掌握综合流程和方法，全芯片综合以及静态时序分析策略；
3. 熟悉Shell/TCL/Perl/Pytho程序；
4. 具备实现Chip DFT的规划能力，包括扫描、边界扫描，MemBIST，MemRepair等，对常用的可测性设计方法如BIST, SCAN,JTAG ATPG有深刻的理解；
5. 掌握熟悉静态时序分析和与后端一起进行时序收敛的方法和策略
6. 对于基于低功耗电源域的中后端流程有过产品级经验
7. 熟悉Cadence系列后端工具为一个好的附加项
More
数字IC设计工程师（STA&DFT）
上海 | 5-10年 | 本科以上 | 2026-09-30

55-85k·15薪 򀀩
芯片前中端工程师（Synthesis/STA/DFT）岗位
上海 | 不限经验 | 本科以上 | 2026-09-30

55-85k·15薪 򀀩

上海 dft salary

Most common salary

30-50K

vs last year

How much does 上海 dft pay? 30-50K is the most common

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