soc设计经理岗位职责

Responsibilities:
Lead team and/work as individual contributto design implement the company’s cutting-edge SoCs, includes:
- SoC partitioning interface definition
- Block level design, RTL coding, verification
- Design reviews verification coverage analysis
- Run Synthesis, formal check, STA; Coordinating backend design, FPGA emulation silicon bring up
Qualification:
- MSEE /MSCE with 6+ years (10+ years fmanager) experience on IC design, equivalent
- Strong skill on Verilog HDL, matlab/C/C++
- Multiple projects experience on IC design from specification to netlist.
- Experience on SoC hardware/software co-design, verification, debug, bring up, strong analysis problem-solving capability
- Wellganized, strong communication skill, work smart, resultiented
- Experience on one more of the following is a plus:
a) Architecture design, partition, integration of multi-core RISC DSP
b) low power design verification, Analog/digital interface design, mixed signal simulation
c) Various SoC components, such as CPU, DSP, GPU, NPU, bus matrix, ISP, audio/video codec, LPDDR3/4/5, PCIe, SDIO/eMMC, USB, MIPI, security, etc

Responsibilities:
Lead team and/work as individual contributto design implement the company’s cutting-edge SoCs, includes:
- SoC partitioning interface definition
- Block level design, RTL coding, verification
- Design reviews verification coverage analysis
- Run Synthesis, formal check, STA; Coordinating backend design, FPGA emulation silicon bring up

Qualification:
- MSEE /MSCE with 7+ years (10+ years fmanager) experience on IC design, equivalent
- Strong skill on Verilog HDL, matlab/C/C++
- Multiple projects experience on IC design from specification to netlist.
- Experience on SoC hardware/software co-design, verification, debug, bring up, strong analysis problem-solving capability
- Wellganized, strong communication skill, work smart, resultiented
- Experience on one more of the following is a plus:
a) Architecture design, partition, integration of multi-core RISC DSP
b) low power design verification, Analog/digital interface design, mixed signal simulation
c) Various SoC components, such as CPU, DSP, GPU, NPU, bus matrix, ISP, audio/video codec, LPDDR3/4/5, PCIe, SDIO/eMMC, USB, MIPI, security, etc

工作职责：1、负责车载视觉、安防AI方向中小型SoC顶层架构设计、子系统划分、总线拓扑、时钟复位、电源域规划，输出架构方案与设计规范。
2、根据产品需求拆解芯片性能、功耗、面积指标，完成系统级PPA评估、瓶颈分析与架构优化，配合后端完成PPA收敛，满足量产指标。
3、负责外部IP评估、选型、集成、验收，主导IP适配、顶层互连、接口定义，保障各子系统稳定协同工作。
4、协助搭建公司SoC设计流程、评审流程、PPA评估规范，沉淀设计方法论，提升团队研发标准化程度。
5、负责SOC设计团队管理以及上下游部门之间的交付和协作
任职资格：1、本科及以上学历，微电子、集成电路、计算机、电子通信等相关专业。
2、5年以上SoC数字设计经验，2年以上团队管理经验，具备完整芯片从定义到流片量产经验。
3、熟悉常规SoC架构，掌握总线、存储、接口、多媒体、ISP等常用IP集成方式；有28nm/40nm工艺流片经验优先。
4、了解芯片PPA评估逻辑，具备模块级、系统级功耗、性能、面积优化实战经验。
5、熟练使用主流IC设计EDA工具，熟悉前端至后端基本流程，能看懂流程报告、指导团队优化。
6、有车载视觉、安防IPC、AI边缘芯片经验者优先；了解AEC-Q100、ISO26262车规规范加分。
7、具备良好沟通协调、风险判断、问题攻坚能力，适配初创研发团队节奏。