晶晨半导体 engineer jobs (salary & requirements)

晶晨半导体 engineer salary range: 20K - 50K, where 90% of positions earn ¥30-50K以上

10% 20-30K ***  ? 30-50K ***  ? 50K以上

晶晨半导体 engineer salary range: 20K-50K, the most positions earn 30-50K, based on 10 related positions in the past year, as of 2026-09-25

￥30-50K以上

90% of positions earn

Note: the average salary is analyzed based on job postings published by the company. We recommend reviewing it together with position type, education, region and experience.

晶晨半导体 engineer salary changes over the years

Note: the data depends on salary samples of online job postings in the corresponding years and does not fully represent the actual situation within the company. For reference only.

Education requirements: 本科 is the most common

70% 本科 30% 硕士

What education does 晶晨半导体 require for engineer positions? 本科占比最多，占70%，硕士占30%

Salary by education

晶晨半导体 engineer salaries by education: 本科 ¥40.7K, 硕士 ¥40.0K.

Experience requirements: 5-10年 is the most common

40% 3-5年 50% 5-10年 10% 不限

What experience does 晶晨半导体 require for engineer positions? 5-10年占比最多，占50%，3-5年占40%，不限占10%

Salary by experience

晶晨半导体 engineer salaries by experience: 3-5年 ¥36.3K, 5-10年 ¥44.0K.

晶晨半导体 engineer hiring regions: mainly 上海, 南京

In which cities does 晶晨半导体 have offices for engineer positions? The main distribution is as follows: 上海 accounts for 70%. Click this module to view the proportions of other cities, based on job postings in the past year. For reference only.

晶晨半导体 engineer hiring trends over the years

晶晨半导体 engineer changes in hiring volume over the years

What does 晶晨半导体 engineer do

Based on related job postings of 晶晨半导体 in the past year

codec design engineer-XA
西安-雁塔区 | 5-10年 | 硕士以上 | 2026-08-29
30-40k

工作职责:
负责视频编解码器相关ip实现。
RTL数字设计和IP集成。
参与模块级和系统级验证。
设计规范的文件和审查。

任职资格:
电气工程硕士/博士，至少3年相关工作经验。
有视频编码器/解码器相关模块经验。
熟悉视频压缩算法和视频压缩标准。
•熟练使用Verilog/System Verilog进行RTL设计。
•有C/ c++经验，Perl优先。
有OVM/UVM经验者优先。
良好的解决问题和沟通能力。
More
AI Framework engineer
上海-浦东新区 | 不限经验 | 本科以上 | 2026-08-29

25-35k 򀀩
SI/PI Engineer
上海 | 3-5年 | 本科以上 | 2025-12-16

30-60k·14薪 򀀩
Codec design engineer-成都(J11356)
成都-高新区 | 3-5年 | 硕士以上 | 2025-12-16

20-40k 򀀩
Digital Design Engineer
上海 | 5-10年 | 本科以上 | 2026-06-06

35-65k·14薪 򀀩
Product Quality Engineer
上海 | 3-5年 | 本科以上 | 2026-08-16

？ 򀀩
Codec design engineer-上海（J11139）
上海-浦东新区 | 5-10年 | 硕士以上 | 2026-08-29

？ 򀀩
PQ Engineer-南京（J11612）
南京-建邺区 | 5-10年 | 本科以上 | 2026-08-29

？ 򀀩

北京 engineer salary

Most common salary

30-50K

vs last year

How much does 北京 engineer pay? 30-50K is the most common

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晶晨半导体 engineer jobs (salary & requirements)

晶晨半导体 engineer salary changes over the years

Education requirements: 本科 is the most common

Salary by education

Experience requirements: 5-10年 is the most common

Salary by experience

晶晨半导体 engineer hiring regions: mainly 上海, 南京

晶晨半导体 engineer hiring trends over the years

What does 晶晨半导体 engineer do

codec design engineer-XA

AI Framework engineer

SI/PI Engineer

Codec design engineer-成都(J11356)

Digital Design Engineer

Product Quality Engineer

Codec design engineer-上海（J11139）

PQ Engineer-南京（J11612）

北京 engineer salary

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